Looking to address a verification challenge that is compared to navigating through London's traffic on a bad day, Cadence Design Systems has launched the Perspec System Verifier platform
The platform brings together an intuitive graphical specification of system level verification scenarios and a definition of the SoC topology and actions. It is said by the company to automate system level coverage driven test development using constraint solving technology. An increase in productivity of up to ten times is claimed over manual test development. The increase in productivity is said to help designers to reproduce, find and fix complex bugs to improve overall SoC quality.
Frank Schirrmeister, pictured, director of product management and marketing in the Cadence System and Verification Group, said: "We are seeing shifts in verification approaches from 'brute force' to hardware verification logic to metric driven. This new platform adds scenario and software driven verification.
"Verification is like navigating through London's traffic," he noted. "You need to know which streets are one way, what difference the time of day makes and so on. It's the same in the chip world."
Perspec requires users to create abstract description in C to test various scenarios. "The output," said Schirrmeister, "is a set of tests which can run on a range of platforms, including FPGA based verification. It enhances top down testing."
Amongst Perspec's features are:
* A UML based view of system level actions and resources that creates a view of complex and hard to test interactions
* Solver technology to automate the generation of portable tests, and
* Tests that run on all pre silicon verification platforms.
Concluding, Schirrmeister said: "Perspec allows you to take two use cases, assess them and generate tests to make sure that, for example, cache coherency works during the power up and power down cycles."
Author
Graham Pitcher
Source: www.newelectronics.co.uk