In a move that enables chip companies to emulate designs with up to 9billion gates, Cadence Design Systems has unveiled the Palladium Z1 enterprise emulation platform. The device, described as the industry’s first datacentre class emulation system, is said to be capable of delivering up to 5x greater emulation throughput than its predecessor.
“The Palladium Z1 platform is capable of executing up to 2304 parallel jobs and has been designed to scale up to more than 9bn gates,” said Michal Siwinski, vice president of Cadence’s system and verification group. “Our customers have told us that 2bn gates is not sufficient, hence our decision to go to 9bn.”
Using a rack based blade architecture means the Palladium Z1 has a 92% smaller footprint and 8x better gate density than the previous platform, while Cadence claims that it offers 4x better user granularity than its nearest competitor. It also offers users a virtual target relocation capability and payload allocation into available resources at run time, avoiding recompiles.
It uses less than one third of the power per emulation cycle of the Palladium XP II platform, achieved by a reduction in power density of up to 44%, an average of 2.5x better system utilisation and number of parallel users, 5x better job queue turnaround time, up to 140million gate per hour compile times on a single workstation, as well as improved debug depth and upload speeds.
Full virtualisation of the external interfaces is available using a virtual target relocation capability and this enables remote access of fully accurate real world devices as well as virtualised peripherals like Virtual JTAG.
Author
Neil Tyler
Source: www.newelectronics.co.uk