Archive : 21 November 2015 год

In a move that enables chip companies to emulate designs with up to 9billion gates, Cadence Design Systems has unveiled the Palladium Z1 enterprise emulation platform. The device, described as the industry’s first datacentre class emulation system, is said to be capable of delivering up to 5x greater emulation throughput than its predecessor.

“The Palladium Z1 platform is capable of executing up to 2304 parallel jobs and has been designed to scale up to more than 9bn gates,” said Michal Siwinski, vice president of Cadence’s system and verification group. “Our customers have told us that 2bn gates is not sufficient, hence our decision to go to 9bn.”

Using a rack based blade architecture means the Palladium Z1 has a 92% smaller footprint and 8x better gate density than the previous platform, while Cadence claims that it offers 4x better user granularity than its nearest competitor. It also offers users a virtual target relocation capability and payload allocation into available resources at run time, avoiding recompiles.

It uses less than one third of the power per emulation cycle of the Palladium XP II platform, achieved by a reduction in power density of up to 44%, an average of 2.5x better system utilisation and number of parallel users, 5x better job queue turnaround time, up to 140million gate per hour compile times on a single workstation, as well as improved debug depth and upload speeds.

Full virtualisation of the external interfaces is available using a virtual target relocation capability and this enables remote access of fully accurate real world devices as well as virtualised peripherals like Virtual JTAG.

Author
Neil Tyler

Source:  www.newelectronics.co.uk

Two power and cost optimised communication processors from CEVA have been designed to address the growing demand for multimode connectivity solutions for Internet of Things and M2M applications.

The CEVA-XC5 and CEVA-XC8 DSP vector processors are the smallest and most power-efficient members of the CEVA-XC architecture, supporting a range of emerging cellular protocols, including LTE MTC Cat-1, Cat-0 or Cat-M. The cores also work with low power wide area network (LPWAN) standards such as LoRA, SigFox and Ingenu.

In particular, CEVA sees opportunities in the cellular sector. “There were 250million cellular connections in 2014,” said Emmanuel Gresset, business development manager, “and this is expected to grow to 2billion by 2020, with the transition to LET and refarming pressure.”

CEVA sees growing demand for such cores. Gresset said the challenge was to develop a core with extremely low power consumption and low cost. “This required an efficient compute system where the PHY/protocol can run on the same processor to minimise latency and reduce time to market. Compared with previous cores, these consume 70% less dynamic power and are 40% smaller.”

The cores feature eight way VLIW vector units. The single unit in the XC5 runs 16MACs per cycle, with the twin units in the XC8 double this to 32MACs/cycle. Each has a four way associative cache, along with a power scaling unit (PSU) which Gresset pointed out is ‘key for IoT applications’. “It allows users to take advantage of LTE Cat-0 and Cat-M.”

The PSU supports multiple clock sources, with the ability to shut down blocks. It also manages the memory subsystem and the Level 1 caches. Multiple voltage domains are also supported. According to CEVA, the PSU can reduce dynamic power consumption during Cat-0 extended discontinuous reception and power saving modes by up to 70%.

Gresset noted the cores are already being designed in by lead customers and added other companies are studying them. “There has been huge demand for cores like these,” he concluded, “and I believe they will be very popular for low end IoT applications.”

Author
Graham Pitcher

Source:  www.newelectronics.co.uk