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FPGA design iterations reduced with new engine

 
Electronics News
9 years ago

FPGA design iterations reduced with new engine


Altera says its Spectra-Q engine will accelerate design productivity and time to market for those working with next generation programmable devices.

Alex Grbic, senior director of software and IP marketing, said: "Spectra-Q will offer a significant productivity improvement for FPGA designers. It is a game changing combination of software technologies that accelerates the design process by reducing designs iterations, while continuing to deliver the industry's fastest compile times."

The engine also features a hierarchical database that enables users to preserve placement and routing information of IP blocks while making changes in other parts of the design.

Albert Chang, pictured, manager of software and DSP product marketing, said: "Design complexity continues to grow with each generation, but there will be a big jump with Generation 10. There are also more than 50 serial protocols in use, as well as embedded ARM cores, which means we need to boost productivity. While we have been able to stay ahead, we want to get further ahead with Generation 10."

The problem is exacerbated, said Chang, by the need for more design iterations, faster time to market and the need to involve hardware and software designers. Spectra-Q is said to reduce the number of iterations through advanced I/O and timing closure, while providing higher levels of abstraction for design entry.

On top of Spectra-Q is a design tool called BluePrint that allows designers to perform architectural exploration and to assign interfaces with greater efficiency. "BluePrint allows 'drag and drop of interfaces to legal locations," Chang noted. "If you're using PCIe, the floorplan will show where it can go and fit it. Previously, it has taken designers two or three months to do this."

Author
Graham Pitcher

Source:  www.newelectronics.co.uk


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