Electronics News
Archive : 7 July 2008 год
Linear Technology announces the LTC3564, a 2.25MHz, synchronous buck regulator that can deliver up to 1.25A of continuous output current from a 2mm x 3mm DFN or ThinSOT package. Using a constant frequency current mode architecture, the LTC3564 operates from an input voltage range of 2.5V to 5.5V, making it dedicated for Li-Ion battery inputs as well as 3.3V or 5V inputs for point-of-load applications. It can generate output voltages as low as 0.6V, enabling it to power the latest generation of low voltage DSPs and microcontrollers. It utilizes a constant 2.25MHz switching frequency, enabling the use of ceramic capacitors and inductors less than a 1mm in height.
The chip uses internal switches with an RDS(ON) of 0.15Ohm (N-Channel and P-Channel) to deliver efficiencies as high as 96%. It also has low dropout 100% duty cycle operation to extend battery run-time. The LTC3564 utilizes automatic Burst Mode operation to achieve 20uA of no load quiescent current and less than 1uA in shutdown. Other features include ±2% output voltage accuracy, current mode operation and over-temperature protection.
The LTC3564EDBC is available in a 2mm x 3mm DFN-6 package while the LTC3564ES5 is available in a 5-lead ThinSOT package. Pricing starts at $1.95 each for both parts in 1,000-piece quantities. The LTC3564IDBC and LTC3564ISS are both tested and guaranteed to operate from a -40°C to 125°C junction temperature. They are both priced at $2.24 in 1,000-piece quantities.
The family includes three members, with capacities from 5K to 17K 4-input Look Up Tables (LUTs). Embedded Block RAM is provided with up to 276Kbits on-chip in 18Kbit dual-port blocks. For small scratch pad memories, LUTs also can be converted into small, distributed memory blocks. To support increasingly common DSP applications, up to 5 sysDSP blocks provide hardwired, high-performance pipelined multiply and accumulate functions. The devices have up to four Phase Locked Loops (PLLs) that allow designers to align and synthesize clocks as required in their designs.
Recognizing that power consumption is a critical concern for system designers, Lattice designed the LA-LatticeXP2 family to use a 1.2-volt core voltage for low power consumption. I/O capacities for the family range from 86 to 358 pins. Flexible I/O buffers support the most popular I/O standards, including LVCMOS, SSTL, HSTL and LVDS. These buffers are supported by pre-engineered I/O logic that simplifies the implementation of Double Data Rate (DDR) and source synchronous standards. This combination provides support for DDR2 memory interfaces at 400Mbps, high performance ADC/DACs at up to 750Mbps and 7:1 LVDS display interfaces at above 600Mbps. LA-LatticeXP2 devices are available in thin Fine Pitch Ball Grid Array (ftBGA) packages as well as popular TQFP and PQFP options.
Flash memory blocks are embedded within LA-LatticeXP2 FPGAs to store the device configuration, providing a true single chip solution that Lattice calls the flexiFLASH architecture. At power up or on user command, the data stored in the Flash memory is transferred into SRAM cells that control the configuration of the device. This transfer is done in a massively parallel fashion, enabling the device logic to be available in approximately 1mS, well ahead of the other devices in the system and much faster than SRAM-based FPGAs that use external boot PROMs, regardless of whether they are provisioned separately on-board or stacked in the same package. This instant-on capability is critical for many system functions such as power up sequencing, address decoding and reset logic.
By keeping the configuration bitstream on-chip, the LA-LatticeXP2 devices also are inherently more secure than alternative multiple device or multi-chip module solutions. This security is enhanced by configuration read-back protection modes. A 64-bit erase/program lock protects against accidental or unauthorized device programming. A one time programmable (OTP) mode is provided for ultimate protection against unauthorized programming. Optional 128-bit AES encryption can be used to secure programming data being passed into the device. The devices also support up to 276Kbits of FlashBAK memory. This exclusive capability allows Embedded Block RAMs to be initialized at power up from Flash memory. During device operation, designers also can choose to write updated data from the block RAM back into the Flash memory. This provides a method to store data such as Power On Self Test (POST), microprocessor code and calibration data. An additional 0.6 to 2.2Kbits of Flash memory is provided in the form of Serial TAG memory for general-purpose use by system designers for storage of device revision data, board identifiers and other data.
Availability and Pricing
Samples of the LA-LatticeXP2 family 5K and 8K LUT devices in 144 TQFP and 256ftBGA, and of the 17K LUT device in the 256ftBGA package, are available now, with 208-PQFP package options available in the third quarter of 2008. The LA-LatticeXP2-5 in the 144 TQFP package will be priced as low as $4.50 in 100,000 unit quantities for delivery in the first half of 2009.
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