While FinFET based chips have finally begun to enter the market, the technology may be too rich for many companies' tastes as the cost-per-function decreases promised by Moore's Law bottom out.
Speaking at a panel during the Design Automation Conference, Scott McCormack, Freescale's director of SoC design, said the team approached its first finFET project 'with an abundance of caution because of the cost [of design]'.
"I don't think it was such a game-changer, but we found a lot more attention to detail was needed, compared to 28nm. We saw a lot of demand on compute resources."
Pressure on server time came from the need to run many more simulations towards the end of the project to check the circuitry would meet timing under different variations of voltage, temperature and process. The use of double patterning to define the routing between transistors – and the effects of random nanometre-scale offsets between masks in a pair – also increased the number of simulated 'corners'. Some companies reported running more than 100 'corners' on their FinFET designs, while those working on older processes, such as 40nm, used fewer than 10.
"We haven't gone through the exercise of reducing the number of corners," McCormack continued. "As the process matures, we can start to move down that path."
Afshin Montaz, senior engineering manager of Broadcom's mixed signal design group, said: "16nm is not for every product or application; the cost per transistor has gone up compared to 28nm, so you may not win on cost. The main advantage of 16nm is speed, which may make sense, or if you want to reduce power drastically."
McCormack agreed: "You don't go into 16nm FinFET to save money: we wanted to differentiate on power. But the cost is a whole new game."
The power advantage of FinFET largely lies in its greatly improved static dissipation. Jayonta Lahiri, vp of engineering in ARM's physical design group, said: "Leakage is much more under control: you really have on/off states again."
Benjamin Mbouombouo, design lead and power solutions architect at Avago, said leakage is 10% of what it was on 28nm. Improved drive currents, compared to the older planar transistor, made it possible to use narrower devices to support high clock speeds, but higher gate capacitance – caused by coupling between the many fins and their surroundings – increases switching power dissipation.
Despite the apparent cost concerns, TSMC technology manager Willy Chen said more companies are signing up for FinFET designs. "We are expecting 50 product tapeouts by the end of this year."
Take one chip and and wait for results
The realisation that silicon dissolves slowly in water could lead to a new class of medical sensor, Professor John Rogers claimed in a keynote at this year's DAC.
Prof Rogers' team has combined silicon with magnesium oxides and silk to build water soluble sensors. One such device, that measures pressure and temperature for monitoring brain injuries, has started testing in rats. Although the team has not yet been able to build wireless transmitters into the devices, molybdenum wires lead from the cranium to an external transmitter.
"The platform is absorbable on the timescale of a week," Prof Rogers said. If successful, the biodegradable sensors will make it possible to avoid the need to perform a second surgery after treatment for brain injuries.
Author
Chris Edwards
Source: www.newelectronics.co.uk