SEGGER has announced added support for the RV32E embedded processor core to its RISC-V floating-point library, which currently supports RV32I.
According to SEGGER this new library will lead to a significant reduction in code size for RISC-V applications using floating point.
With all arithmetic functions hand-coded in assembly language, the memory footprint of RISC-V applications using floating-point code is significantly reduced. The Floating-Point library complies with the RISC-V ABI standard and can be used as a plug-and-play replacement for any other floating point library.
Replacing the GNU floating-point library used by most toolchains with the SEGGER assembly optimised equivalent results, according to SEGGER, in a 72% code size reduction of the benchmark application. The library supports RV32I, as well as the newly introduced RV32E embedded variant of the RISC-V core with the assembly-level code.
"This new release is much smaller than anything available to us for comparison and, at the same time, is incredibly fast,” said Rolf Segger, Founder of SEGGER. "In the world of Embedded Systems, every byte counts. The SEGGER Floating-Point library delivers high performance and uses the architectural advantages of RISC-V to close the code-density gap to comparable Arm Cortex devices.”
The library can be licensed by end customers and toolchain suppliers.
As with the SEGGER Runtime Library, it is integrated into SEGGER Embedded Studio for RISC-V. Using Embedded Studio, benchmarking for both floating-point and runtime libraries can be done quickly and easily. It is readily available at no cost for non-commercial usage under SEGGER’s Friendly License.
Author
Neil Tyler
Source: www.newelectronics.co.uk