While FinFET technology has helped to keep leakage under control as process dimensions shrink, dynamic power consumption remains a major concern.
Looking to provide system designers with a better way to explore dynamic power consumption, Mentor Graphics has released the Veloce Power Application software, said to enable accurate, timely and efficient power analysis at the system, RTL and gate levels in complex SoCs.
Gabriele Pulini, product marketing manager with Mentor's emulation division, noted: "Until now, the industry has been looking at the problem in the wrong way because functional bench testing isn't capturing OS boot and applications activity."
According to Mentor, complex SoCs are now verified using live applications that require the OS to be booted and software to run on an emulator. But when designs with significant software content are run on an emulator, the files created are too large for power analysis tools to handle practically.
The Veloce Power Application replaces the file based power analysis flow with an interface to power analysis tools. The Dynamic Read Waveform API allows information to be captured from the power switching activity plot and transferred to power analysis tools. This, the company adds, enables accurate power calculation at the system level, better power exploration at RTL for power budgeting and tradeoffs as well as more accurate power analysis and sign-off at the gate level.
The result is said to be a significant boost in runtime and performance, with early access customers reporting runtime performance improvements of more than 400%.
Author
Graham Pitcher
Source: www.newelectronics.co.uk