Xilinx, Arm, Cadence Design Systems and TSMC are collaborating to build the first Cache Coherent Interconnect for Accelerators (CCIX) test chip with TSMC 7nm FinFET process technology for delivery in 2018.
The test chip will be implemented on TSMC’s 7nm process and be based on the latest Arm DynamIQ technology, CMN-600 coherent on-chip bus and foundation IP.
According to those companies involved in the collaboration CCIX leverages existing server interconnect infrastructure and is able to deliver higher bandwidth, lower latency and cache coherent access to shared memory delivering a significant improvement in the usability of accelerators and the overall performance and efficiency of data centre platforms, lowering the barrier to entry into existing server systems and improving the total cost of ownership (TCO) of acceleration systems.
Applications such as big data analytics, search, machine learning, wireless 4G/5G, in-memory database processing, video analytics, and network processing benefit from acceleration engines that enable data to be moved seamlessly among various system components.
CCIX will allow components to access and process data irrespective of where it resides, without the need for complex programming environments.
“With the surge in artificial intelligence and big data, we’re seeing increasing demand for more heterogeneous compute across more applications,” said Noel Hurley, vice president and general manager, Infrastructure Group, Arm. “The test chip will not only demonstrate how the latest Arm technology with coherent multichip accelerators can scale across the data centre, but reinforces our commitment to solving the challenge of accessing data quickly and easily. This innovative and collaborative approach to coherent memory is a significant step forward in delivering high-performance, efficient data centre platforms.”
Author
Neil Tyler
Source: www.newelectronics.co.uk