Archive : 22 June 2016 год

The latest RapidIO specification has been released by rapidio.org. The 25xN specification is said to provide an open standard interconnect fabric for those systems requiring heterogeneous coherent scale out and non volatile storage.

“With the release of the 25xN 100Gbit/s RapidIO Specification, our focus now shifts toward our Coherent Scale Out Task Group and our Non-Volatile Storage Task Group,” said Rick O’Connor, executive director of RapidIO.org. “Work on [these] draft specifications is progressing and we invite members of industry to join us and participate in defining these key building blocks for flexible, heterogeneous, coherent scale out of performance critical, low latency applications over RapidIO fabrics.”

RapidIO, which has been developed continuously since 1997, is a scalable, packet-switched high-performance fabric intended address the needs of those designing equipment for the data centre, analytics, wireless infrastructure, edge networking, storage, scientific, military and industrial markets.

“The public release of the 25xN 100Gbit/s RapidIO Specification is the culmination of efforts and contributions of RapidIO.org member companies,” said Paul Carson, chairman of RapidIO.org and director of IP development at Texas Instruments. “This work extends the performance roadmap of RapidIO fabrics for use in heterogeneous systems for many years to come.”

Author
Graham Pitcher

Source:  www.newelectronics.co.uk

A nine axis motion sensor from Bosch Sensortec is said to be suited to applications ranging from smartphones and smart watches to wearable electronics. According to the company, the 2.5 x 3 x 0.95mm package is the smallest of any similar device.

The electronic integrates accelerometer, gyroscope and geomagnetic sensor technologies, while meeting the low power requirements of wearable devices. According to the company, power consumption is less than 1.5mA.

“By combining Bosch Sensortec’s advanced sensor technologies into a single compact package, the BMX160 sets new industry benchmarks for high performance, tiny footprint and low power consumption”, claimed Jeanne Forget, VP of marketing for Bosch Sensortec. “This device overcomes placement constraints in smartphones and directly addresses the demands of wearable devices, where PCB space and low power consumption are at an even greater premium”.

Bosch notes the BMX160 effectively replaces today’s two component solution – a six axis IMU with a three axis geomagnetic sensor. Instead, the part is said to provide placement flexibility, overcoming current limitations on where the magnetic sensor can be placed.

It has a built in power management unit, allowing the application processor to remain in sleep mode for longer, while the accelerometer, gyroscope and magnetic technology have been optimised for low offset, low noise and best temperature stability.

Author
Graham Pitcher

Source:  www.newelectronics.co.uk

In theory, a program running on a 64 core machine, should execute 64 times as quickly as it would on a single core machine. But, according to a team from MIT, it rarely works out that way. Most computer programs are sequential, and splitting them up so that chunks can run in parallel can result in complications.

Researchers from MIT’s Computer Science and Artificial Intelligence Laboratory have created a chip called Swarm, said to make parallel programs more efficient and easier to write.

In simulations, the researchers compared Swarm versions of six common algorithms with the best existing parallel versions, which had been individually engineered. Swarm versions were found to be up to 18 times faster, but generally required only 10% of the code. Not only that, Swarm speeded one program computer scientists had failed to parallelise by a factor of 75.

“Multicore systems are really hard to program,” says Daniel Sanchez, an MIT assistant professor who led the project. “You have to explicitly divide the work that you’re doing into tasks, then you need to enforce some synchronisation between tasks accessing shared data. What this architecture does, essentially, is to remove all sorts of explicit synchronisation to make parallel programming easier.

“There’s an especially hard set of applications that have resisted parallelisation for many years and those are the kinds of applications we’ve focused on.”

Swarm is said to differ from other multicore chips in that it has extra circuitry for handling prioritisation. It timestamps tasks according to their priorities and begins working on the highest priority tasks in parallel. While higher priority tasks may create lower priority tasks of their own, Swarm slots those into its task queue automatically. It will also ensure higher priority tasks run first and will maintain synchronisation between cores accessing the same data.

The hard work is said to be done by the chip itself, which Sanchez designed in collaboration with MIT graduates Mark Jeffrey and Suvinay Subramanian, University of Washington PhD student Cong Yan and MIT Professor Joel Emer, a senior distinguished research scientist with NVidia.

Apart from extra circuitry to store and manage the task queue of tasks, Swarm uses a Bloom filter to record the memory addresses of all the data its cores are currently working on. This helps Swarm to identify memory access conflicts and the team showed that timestamping makes synchronisation between cores easier to enforce.

Finally, all the cores occasionally report the time stamps of the highest priority tasks they’re still executing. If a core has finished tasks that have earlier time stamps than those reported by its fellows, it knows it can write its results to memory without creating conflicts.

Author
Graham Pitcher

Source:  www.newelectronics.co.uk