Archive : 6 May 2015 год

Altium has released version 15.1 of its flagship tool Altium Designer. Included in the release are features intended to improve design efficiency, with expansions to productivity, documentation and high speed design.

"Altium Designer 15.1 is building upon the solid foundation we've had in place since the original release of Altium Designer 15," said Sergey Kostinsky, vp of engineering. "There's incremental improvements upon every layer in the platform for both designers and fabricators alike. This update is a win-win for everyone involved in the design process, with greater accuracy in documentation features for fabricators, to expanded productivity and high-speed enhancements for electronics designers."

New features in version 15.1 focus on improvements to the design ecosystem. High speed design configurations for length matching rules can now be performed using a wizard that automatically accounts for T-branches, components, signal pairs and groups.

PCB designs can be exported as 3D PDFs, allowing anyone with a compatible PDF viewer to view and rotate a design in 3D. Boards can be navigated with individual component selection, providing greater accuracy and design intent to fabricators.

Surface layers for rigid-flex designs can now be added with 'bikini' coverlays that are fully visible in 3D and can be configured with the designer's specific material needs. Coverlay edge clearance and expansion rules have also been added to the design rule options, providing users with precise control over coverlay applications.

A pad and via library allows users to define custom templates for pad shape and size. Templates can then be applied to specific groups of pads on a PCB for easy application, saving countless hours defining pad options individually.

Finally, the addition of a Unions panel is said to help users to better organise design data and to align Union data with other PCB objects. The panel will show a hierarchical view of union types, unions and union primitives for easy reference.

Author
Graham Pitcher

Source:  www.newelectronics.co.uk

Materials scientists at the University of Massachusetts Amherst have investigated how micro-scale wrinkling affects electrical performance in carbon based, single crystal semiconductors and believe the work could have application in wearable electronics.

Post doctoral student Marcos Reyes-Martinez said: "We worked with a crystalline semiconductor called rubrene – a carbon based material that has performance factors, such as charge-carrier mobility, surpassing those measured in amorphous silicon."

According to the team, organic semiconductors are an interesting alternative to silicon; adding that devices based on organic semiconductors do not require high temperatures, clean rooms and expensive processing steps.

Until now, Reyes-Martinez noted, most researchers have focused on controlling the detrimental effects of mechanical deformation on a transistor's electrical properties. However, the team discovered that mechanical deformations only decrease performance under certain conditions, and can actually enhance performance in other cases.

"Our goal was not only to show these effects, but also to explain and understand them," Reyes-Martinez continued. "What we've done is take advantage of the ordered structure of ultra thin organic single crystals of rubrene to fabricate high perfomance, thin-film transistors."

The team found that crystals ranging in thickness from about 150nm to 1µm could be wrinkled and applied to any elastomer substrate. Reyes-Martinez said: "Our experiments are important because they help scientists working on flexible electronic devices to determine performance limitations of new materials under extreme mechanical deformations, such as when electronic devices conform to skin."

Author
Graham Pitcher

Source:  www.newelectronics.co.uk

Sharp Microelectronics has unveiled a 1.33in diagonal colour memory LCD. According to the company, the eight colour module has ultra low power consumption, allowing designers to use it to create 'always on' devices that show data at a glance.

The device is said to deliver smooth graphics and to support simple video, allowing the display of what Sharp calls 'richer graphics than many cholesteric, electrophoretic and other bistable e-ink display solutions'. Transmissivity is said to allow the use of a backlight for visibility in low ambient light.

Author
Graham Pitcher

Source:  www.newelectronics.co.uk

The Embedded Microprocessor Benchmark Consortium (EEMBC) has announced a benchmark that looks at the efficiency of Internet of Things edge nodes. The benchmark, currently in development, aims to provide a standardised way for application developers to compare the efficiency of systems targeted at IoT end point applications.

"EEMBC's IoT benchmark will build upon the measurement platform and profile approach that we developed for ULPBench," said Markus Levy, pictured, EEMBC president. "We're excited from an engineering perspective, because incorporating additional performance and efficiency aspects into the measurement system, specifically the wireless and sensing pieces, presents some interesting technical challenges."

According to EEMBC, such edge nodes have four primary parts: sensors or transducers; processing; interfaces; and a communication mechanism. Its benchmark will provide a method to determine the combined energy consumption of the platform, taking real world effects into consideration. This approach is said to enable the optimised selection of the MCU and RF elements.

Current working group members include Analog Devices, ARM, Freescale, Imagination, Microchip, NXP, Silicon Labs, STMicroelectronics, Synopsys, and Texas Instruments.

Author
Graham Pitcher

Source:  www.newelectronics.co.uk

Microarchitectural improvements applied in ARM's Cortex-A72 core are said to increase efficiency such that it can deliver the same performance of a Cortex-A15 processor while consuming half the power on a 28nm process. And the company suggests the A72 will consume 75% less power when manufactured on 14/16nm FinFET nodes. 

In a blog post, Brian Jeff, director of product marketing for the Cortex-A cores, said the performance of a Cortex-A15 CPU can be reproduced on the Cortex-A72 processor at reduced frequency and voltage resulting in a dramatic power reduction. "However," he noted, "mobile apps often push the CPU to maximum performance, rather than a specific absolute required level of performance. In this case, a 2.5GHz Cortex-A72 CPU consumes 30 to 35% less power than the 28nm Cortex-A15 processor, whilst still delivering more than twice the peak performance."

The Cortex-A72 microarchitecture features a new branch prediction unit said to reduce overall power consumption, whilst improving performance across a range of benchmarks. The instruction cache has been also redesigned to optimise tag look up. Meanwhile, the decode block has undergone what Jeff calls 'extensive decoder power optimisation'.

In the pipeline's dispatch/retire section, the effective dispatch bandwidth has been increased to a five wide dispatch, offering increased performance, while reducing decode power. Architectural and speculative register files have also been optimised to reduce ports and area.

Lower latency floating point functional units have also been integrated. Jeff noted: "These are very fast floating point latencies, comparable with the latest high performance server and PC CPUs. Floating point latency is important in typical mobile and consumer use cases, where there is commonly a mix of FP and integer work. In these settings, the latency between computation and result is critical. Shorter latencies mean integer instructions waiting on the results of those instructions are less likely to be stalled."

According to ARM, the improvements show an increase of around 25% in SpecFP and SpecFP2006 benchmark scores.

Jeff noted the A72 featured: performance improvements in key areas; generational performance upside across all workload categories; and power efficiency improvements throughout the microarchitecture. The result, he concluded, is a reduced area, lower cost solution.

Author
Graham Pitcher

Source:  www.newelectronics.co.uk