Archive : 24 February 2015 год

Microsoft is using Altera Arria 10 FPGAs to boost performance/Watt in data centre acceleration applications based on convolutional neural network (CNN) algorithms, used for image classification, image recognition, and natural language processing.

Engineering samples of Arria 10 FPGAs are said to offer up to 40 GFLOPS/W; more than three times that offered by GPUs. This performance is achieved through using OpenCL to code the Arria 10 FPGA and its IEEE754 hard floating point DSP blocks.

“We are seeing a significant leap forward in CNN performance and power efficiency with Arria 10 engineering samples and the silicon's precision hard floating point in the DSP blocks is part of the reason we are seeing compelling results in our research," said Doug Burger, director, Client and Cloud Apps, Microsoft Research.

Author
Graham Pitcher

Source:  www.newelectronics.co.uk

In a move that significantly broadens its portfolio, Xilinx has unveiled the UltraScale+ family of FPGAs, 3D ICs and MPSoCs. The UltraScale portfolio now spans 20nm and 16nm FPGA, SoC and 3D ICs, with TSMC's 16FF+ 3D transistors said to bring a 'significant' boost in performance/Watt.

Giles Peckham, EMEA marketing director, said: "The UltraScale+ portfolio offers a range of new capabilities that look to address the challenges customers tell us they face, such as performance and power scalability, systems integration and greater intelligence, as well as security, safety and reliability. As a result, we expect these additions will significantly expand the markets we are able to address."

Those markets are expected to include next generation applications such as LTE Advanced and early 5G, terabit wireless communications, automotive and industrial IoT.

Amongst the improvements to the family are: UltraRAM, which can replace the need for external memory; and SmartConnect, an intelligent optimisation technology.

Meanwhile, Zynq UltraScale+ MPSoCs offer heterogeneous multiprocessing, based on a quad core Cortex-A53 and a dual core Cortex-R5 for real time applications.

Author
Graham Pitcher

Source:  www.newelectronics.co.uk

Responding to increasing data traffic loads, EZchip has unveiled the TILE-Mx multicore processor family, featuring 100 ARMv8-A 64bit cores. Targeted at high performance network applications and network functions virtualization (NFV), the launch follows EZchip's acquisition of Tilera last year.

Called the TILE-Mx, the device – scheduled to sample in 2016 – is built around the Cortex-A53 core and is optimised for data-path throughput and combining high performance management and control-plane processing.

Offering a processing performance of 200Gbit/s, the device will be accompanied by two further members of the family, with 64 and 36 cores.

“We are bringing to the market a new type of highly differentiated multicore processor, leveraging the best from EZchip's and Tilera's technologies, and specifically architected to address the next generation of high-performance data center, cloud and carrier networks," said Eli Fruchter, CEO of EZchip. “The combination of EZchip's and Tilera's market-proven leading technologies enables us to develop a new multicore processors family that uniquely integrate powerful networking capabilities together with the highest number of processor cores to address a wide range of applications and market segments."

Author
Graham Pitcher

Source:  www.newelectronics.co.uk