Electronics News
Archive : 28 March 2008 год
09:04Miniature photocoupler in SDIP
Toshiba Electronics Europe (TEE) has launched a miniature photocoupler that delivers the same isolation and current outputs as previous DIP packaged devices in a form factor that is 50% smaller. The TLP700 has an isolation voltage of 5000Vrms and a common mode transient immunity rating of ±10kV/µs. Suitable for use in IGBT and power MOSFET gate drive circuits, the device has a peak output current of 2.0A, allowing it to directly drive some low power IGBTs up to around 50A. Operating with a supply voltage of between 15V and 30V, the TLP700 keeps power consumption to a minimum through a maximum supply current of 2mA. Maximum switching time is rated at 500ns. The photocoupler comprises a GaAlAs infrared LED and a photodetector IC in the SDIP six-pin packaging measuring 6.8mm x 4.58mm x 3.65mm. The device has been designed to meet the requirements of all relevant international safety approvals and delivers guaranteed performance at temperatures between -40°C and 100°C.
Source: www.channel-e.biz
09:02Low-Power SRAM with 64 Mbit and 32 Mbit
Renesas announced the development of the R1WV6416R Series of 64 Mbit Advanced Low-Power SRAM (Advanced LPSRAM) and the R1LV3216R Series of 32 Mbit Advanced LPSRAM products with compact chip size. Sample shipments of the 32 Mbit products will begin in April 2008, and of the 64 Mbit products in July, in Japan. These two They will be available in different packages and specifications, such as access time, for a total of twelve 64 Mbit products and eight 32 Mbit products to meet a wide range of requirements in fields including industry, office equipment, consumer electronics, automotive systems, and communications equipment. To accommodate a variety of applications, these two series are being offered in several different packages: TSOP I (48-pin), μTSOP (52-pin), and for 64 Mbit products FBGA (48-ball).
The TSOP I and μTSOP packages have the same dimensions as those of previous 16 Mbit products, and the ball layout of the FBGA package is signal pin compatible. Advanced LPSRAM uses a stacked capacitor memory cell configuration, an approach with a proven track record in DRAM cells. It virtually eliminates soft errors caused by alpha radiation or high-energy neutron radiation, which can be a problem with ultrafine SRAM. In addition, this memory cell configuration avoids the unintended formation of an parasitic thyristor, which can generate spurious current flows and cause latchups. Advanced LPSRAM products currently in mass production include 4 Mbit and 16 Mbit products, as well as 32 Mbit products comprising two 16 Mbit chips stacked in a single package. The two new series respond to demand for increased capacity with compact single-chip 32 Mbit products and 64 Mbit products comprising two 32 Mbit chips stacked in a single package.
The R1WV6416R Series of 64 Mbit Advanced LPSRAM products and the R1LV3216R Series of 32 Mbit Advanced LPSRAM products are available with access times of 55 ns (nanoseconds) or 70 ns, and in TSOP I (48-pin), μTSOP (52-pin), or (for 64 Mbit products) FBGA (48-ball) packages. The package of the TSOP I (48-pin) products is identical to that of current 16 Mbit products, and the package of the μTSOP (52-pin) is identical to that of current 8 Mbit, 16 Mbit, and 32 Mbit products. FBGA (48-ball) products have a ball layout that is backward compatible with that of current 4 Mbit, 8 Mbit, 16 Mbit, and 32 Mbit products. Advanced LPSRAM eliminates soft errors through the use of stacked capacitors and reduces the surface area of each memory cell by employing a vertical configuration in which the stacked capacitors are formed in a layer above the transistors.
The SRAM cells use polysilicon TFTs*5 as P-channel load transistors. By forming these in a layer above the other transistors and reducing the number of transistors underneath, the memory cell surface area is reduced. This is why the 32 Mbit R1LV3216R Series has the smallest chip size in the industry for a 32 Mbit low-power SRAM product. Furthermore, Advanced LPSRAM requires no refreshes and therefore uses less power than pseudo SRAM (PSRAM), which uses SDRAM or DRAM memory cells as the SRAM interface. This makes it suitable for low-power applications that use batteries for data backup.
The TSOP I and μTSOP packages have the same dimensions as those of previous 16 Mbit products, and the ball layout of the FBGA package is signal pin compatible. Advanced LPSRAM uses a stacked capacitor memory cell configuration, an approach with a proven track record in DRAM cells. It virtually eliminates soft errors caused by alpha radiation or high-energy neutron radiation, which can be a problem with ultrafine SRAM. In addition, this memory cell configuration avoids the unintended formation of an parasitic thyristor, which can generate spurious current flows and cause latchups. Advanced LPSRAM products currently in mass production include 4 Mbit and 16 Mbit products, as well as 32 Mbit products comprising two 16 Mbit chips stacked in a single package. The two new series respond to demand for increased capacity with compact single-chip 32 Mbit products and 64 Mbit products comprising two 32 Mbit chips stacked in a single package.
The R1WV6416R Series of 64 Mbit Advanced LPSRAM products and the R1LV3216R Series of 32 Mbit Advanced LPSRAM products are available with access times of 55 ns (nanoseconds) or 70 ns, and in TSOP I (48-pin), μTSOP (52-pin), or (for 64 Mbit products) FBGA (48-ball) packages. The package of the TSOP I (48-pin) products is identical to that of current 16 Mbit products, and the package of the μTSOP (52-pin) is identical to that of current 8 Mbit, 16 Mbit, and 32 Mbit products. FBGA (48-ball) products have a ball layout that is backward compatible with that of current 4 Mbit, 8 Mbit, 16 Mbit, and 32 Mbit products. Advanced LPSRAM eliminates soft errors through the use of stacked capacitors and reduces the surface area of each memory cell by employing a vertical configuration in which the stacked capacitors are formed in a layer above the transistors.
The SRAM cells use polysilicon TFTs*5 as P-channel load transistors. By forming these in a layer above the other transistors and reducing the number of transistors underneath, the memory cell surface area is reduced. This is why the 32 Mbit R1LV3216R Series has the smallest chip size in the industry for a 32 Mbit low-power SRAM product. Furthermore, Advanced LPSRAM requires no refreshes and therefore uses less power than pseudo SRAM (PSRAM), which uses SDRAM or DRAM memory cells as the SRAM interface. This makes it suitable for low-power applications that use batteries for data backup.
Source: www.channel-e.biz
09:01Battery authentication ICs
Intersil has introduced a battery authentication ICs for cell phones. The ISL9206 and ISL9206A are battery authentication ICs that incorporate Intersil’s FlexiHash+ engine. It provides very high levels of security using a basic challenge/response scheme based on 32-bit challenge code and 8-bit response code. FlexiHash+ employs two sets of 32-bit secrets for generating authentication code to offer tens of billions of potential configurations for users. And with 16x8 one-time programmable (OTP) ROM, the devices can store a total of three sets of these 32-bit secrets. Programmable memory adds the ability to store up to 48 bits of ID code and/or pack information. The result is fast, highly secure and flexible battery/device authentication that makes hacking prohibitively difficult due to the exhaustive key search that would be needed to break a code.
The ISL9206/06A each have an operating voltage range from 2.6V to 4.8V and can be powered directly from a one-cell li-Ion/li-Polymer or a three-cell series NiMH battery pack. The devices can also be powered by the XSD bus when the bus pull-up voltage is 3.3V or higher. They connect to the cell terminals of a battery pack and include an on-chip voltage regulation circuit, POR and a non-crystal based oscillator for bus timing reference. Both new authentication ICs also include a clone prevention feature offering safety and revenue protection suitable for protection against after-market replacements. As an added feature, the ISL9206 incorporates multi-pass authentication that can be used to maximise security. Both devices are also design choices for a variety of printer cartridges. The ISL9206 and ISL9206A are available now in 5 Ld SOT-23 and 8 Ld TDFN packages.
The ISL9206/06A each have an operating voltage range from 2.6V to 4.8V and can be powered directly from a one-cell li-Ion/li-Polymer or a three-cell series NiMH battery pack. The devices can also be powered by the XSD bus when the bus pull-up voltage is 3.3V or higher. They connect to the cell terminals of a battery pack and include an on-chip voltage regulation circuit, POR and a non-crystal based oscillator for bus timing reference. Both new authentication ICs also include a clone prevention feature offering safety and revenue protection suitable for protection against after-market replacements. As an added feature, the ISL9206 incorporates multi-pass authentication that can be used to maximise security. Both devices are also design choices for a variety of printer cartridges. The ISL9206 and ISL9206A are available now in 5 Ld SOT-23 and 8 Ld TDFN packages.
Source: www.channel-e.biz