Electronics News
Archive : 1 November 2007 год
09:47SMD IR receiver
Vishay released a series of surface-mount infrared receiver modules. Designed for long-range operation in infrared remote control, data transmission, and light barrier applications, the TSOP85 series is intended for use in portable systems requiring ultra-small component profiles. Typical end products include small handheld devices, such as laptops, digicams and video equipment, music and video players, and navigation equipment. In optical modules, decreasing the package size results in a reduction of lens size, which therefore reduces sensitivity and range. The series, however, neutralizes this effect through the addition of a second lens and photodiode.
In addition, the two-lens arrangement achieves a broader receiving angle than can be achieved with only one lens. The receiver module combine two photo detectors and a preamplifier in a top- or side-view surface mount package. The devices offer a footprint with a height of 3.3 mm in top view and only 2.74 mm in side view. In addition to being specified for a supply voltage range of 2.7 V to 5.5 V, the series contains versions capable of operating with short-burst ( ≥ 6 cycles/burst) transmission codes and data rates up to 4000 bit/s, and versions exhibiting immunity to even severe environmental noise. All devices in the series are available in seven standard carrier frequencies from 30 kHz up to 56 kHz and contain internal Automatic Gain Control (AGC) circuitry, providing enhanced immunity against optical noise and other ambient disturbances.
In addition, the two-lens arrangement achieves a broader receiving angle than can be achieved with only one lens. The receiver module combine two photo detectors and a preamplifier in a top- or side-view surface mount package. The devices offer a footprint with a height of 3.3 mm in top view and only 2.74 mm in side view. In addition to being specified for a supply voltage range of 2.7 V to 5.5 V, the series contains versions capable of operating with short-burst ( ≥ 6 cycles/burst) transmission codes and data rates up to 4000 bit/s, and versions exhibiting immunity to even severe environmental noise. All devices in the series are available in seven standard carrier frequencies from 30 kHz up to 56 kHz and contain internal Automatic Gain Control (AGC) circuitry, providing enhanced immunity against optical noise and other ambient disturbances.
Source: www.channel-e.biz
09:46SPI host controller in the QuickLogic library
QuickLogic announces the addition of a SPI (serial peripheral interconnect) Host Controller to its customer specific standard product (CSSP) functional library. The SPI interface gives mobile device designers a low pin-count alternative to SDIO or mini-PCI for implementing high speed connections to wireless modules and other peripheral functions. QuickLogic's CSSP approach blends fixed logic blocks with an array of low-power customisable building blocks (CBBs) for implementing additional standards-based or custom functions. This approach offers development teams a customisable platform that addresses the need to meet cost, battery life and PCB-space requirements, while also maintaining the flexibility to evolve designs as market demands change in the future. QuickLogic's CSSP platforms include the PolarPro and ArcticLink platform families, offering a range of options in size and capacity.
When implemented in QuickLogic's programmable platform products, an SDIO Host Controller requires 15 customisable building blocks (CBBs), and PCI requires 6 to 9 CBBs depending on the configuration. The SPI Host Controller requires three CBBs and four I/Os, freeing resources on the CSSP platform for the implementation of additional functions (devices with from 8 to 240 CBBs are available in QuickLogic's range). The SPI interface is capable of operating at clock rates to 52 MHz. It comes with a low-overhead SPI software driver that can be customised for specific peripherals for higher performance.
When implemented in QuickLogic's programmable platform products, an SDIO Host Controller requires 15 customisable building blocks (CBBs), and PCI requires 6 to 9 CBBs depending on the configuration. The SPI Host Controller requires three CBBs and four I/Os, freeing resources on the CSSP platform for the implementation of additional functions (devices with from 8 to 240 CBBs are available in QuickLogic's range). The SPI interface is capable of operating at clock rates to 52 MHz. It comes with a low-overhead SPI software driver that can be customised for specific peripherals for higher performance.
Source: www.channel-e.biz
09:43FPGA solution for SPAUI to SPI4.2
Lattice Semiconductor and Dune Networks, a provider of networking devices for Data Center, Enterprise and Carrier Ethernet scalable switching platforms, will collaborate in the development and marketing of SPAUI-based networking solutions. LatticeSCM FPGAs provide a programmable platform to bridge to switch fabrics and traffic managers by utilizing hardened Ethernet and SPI4.2 blocks implemented via exclusive Masked Array for Cost Optimization (MACO) technology.
Dune Networks’ FAP traffic managers provide ingress and egress programmable traffic management solutions that address the requirements of the MEF, IETF DiffServ, and DSL Forum TR-059/TR-101. SPAUI is a serial interface based on the10GbE XAUI and SPI4.2 standards. By combining the benefits of both into one comprehensive standard, SPAUI enables system designers to take advantage of the ubiquity of XAUI as a physical layer as well as the multi-channel QoS and flow control mechanisms of SPI4.2. SPAUI is also designed to support aggregate rates of higher speeds. SPAUI is one of the interface options of Dune Networks’ SAND chipset. When implemented in a LatticeSCM-15E FPGA in a 256 fine pitch Ball Grid Array (fpBGA) package, the Lattice XAUI to SPI4.2 bridging solution requires a mere 17mm x 17mm on a printed circuit board while consuming 2.5Watts of power.
About SPAUI
SPAUI, an interface based on the XAUI industry standard, incorporates several extensions that provide 10Gbps applications with speedup (for packet headers, full rate 12GE), channelization, packet interleaving and refined flow control. SPAUI is implementation-friendly, backward compatible to standard XAUI and ideal for dense 10GE and higher speed Ethernet solutions. The SPAUI memorandum is available upon request from Dune Networks at no cost.
Dune Networks’ FAP traffic managers provide ingress and egress programmable traffic management solutions that address the requirements of the MEF, IETF DiffServ, and DSL Forum TR-059/TR-101. SPAUI is a serial interface based on the10GbE XAUI and SPI4.2 standards. By combining the benefits of both into one comprehensive standard, SPAUI enables system designers to take advantage of the ubiquity of XAUI as a physical layer as well as the multi-channel QoS and flow control mechanisms of SPI4.2. SPAUI is also designed to support aggregate rates of higher speeds. SPAUI is one of the interface options of Dune Networks’ SAND chipset. When implemented in a LatticeSCM-15E FPGA in a 256 fine pitch Ball Grid Array (fpBGA) package, the Lattice XAUI to SPI4.2 bridging solution requires a mere 17mm x 17mm on a printed circuit board while consuming 2.5Watts of power.
About SPAUI
SPAUI, an interface based on the XAUI industry standard, incorporates several extensions that provide 10Gbps applications with speedup (for packet headers, full rate 12GE), channelization, packet interleaving and refined flow control. SPAUI is implementation-friendly, backward compatible to standard XAUI and ideal for dense 10GE and higher speed Ethernet solutions. The SPAUI memorandum is available upon request from Dune Networks at no cost.
Source: www.channel-e.biz