Looking to meet growing demand for more performance from video processing systems, but with lower energy consumption, Cadence has unveiled the Tensilica Vision P5 digital signal processor (DSP).Looking to meet growing demand for more performance from video processing systems, but with lower energy consumption, Cadence has unveiled the Tensilica Vision P5 digital signal processor (DSP).
The flagship imaging and vision core is said to offer up to 13X better performance than the company’s previous generation device while consuming five times less energy on vision tasks.
Dennis Crespo, director of product marketing for Cadence’s Tensilica group, said: “Cameras are everywhere. While Tensilica has a long history of working with mobile apps, these have mainly been ‘close to camera’. We are now expanding into automotive with this new generation, looking to target vision applications inside and outside of the vehicle.”
The Vision P5 has been developed for applications requiring high memory and operation parallelism, supporting complex vision processing at high resolution and frame rates. Suitable for offloading vision and imaging functions from the main CPU, the device is likely to find application in such areas as image and video enhancement, robotic vision, and face detection and authentication. Other potential applications include object tracking and object avoidance.
“With smaller pixels in cameras,” Crespo noted, “there are more problems to be solved, including noise. Different sensors have different noise patterns, so a DSP is needed for correction, as well as to perform tasks like image stabilisation. Meanwhile, face detection requires depth sensing, which also needs a DSP.”
The core features: a 1024bit memory interface with SuperGather technology; up to four vector ALU operations per cycle, each with up to 64way data parallelism; up to five instructions issued per cycle; an enhanced 8,16 and 32bit ISA tuned for vision/imaging applications; and an optional 16 way IEEE single precision vector floating point processing unit delivering 32GFLOPs at 1GHz.
Crespo said the device can handle 256 ALU operations per cycle, compared to the previous 90, and features 430 additions to the instruction set.
“We have a customer who plans to use an eight core version of the P5, consuming less than 4W, in a scientific computing application,” said Crespo. “This will replace a GPU array consuming 250W.”
According to the company, the P5 can run at clock speeds of 1.1GHz when targeted at a 16nm FinFET process.
Author
Graham Pitcher
Source: www.newelectronics.co.uk